/**
 ******************************************************************************
 * @file    spi.h
 * @author  hyseim software Team
 * @date    18-Aug-2023
 * @brief   This file provides all the headers of the assi_spi functions.
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2020 Hyseim. Co., Ltd.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SPI_H__
#define __SPI_H__

#include "chip_define.h"
#include "common.h"
#include "assi.h"

/* ================================================================================ */
/* ==============          Serial Peripheral Interface (SPI)          ============= */
/* ================================================================================ */
typedef struct
{
    __IO uint32_t CR0;             /*!< Control Register 0,                                  Address offset: 0x000 */
    __IO uint32_t CR1;             /*!< Control Register 1,                                  Address offset: 0x004 */
    __IO uint32_t SPIENR;          /*!< SPI Enable Register,                                 Address offset: 0x008 */
    __IO uint32_t MWCR;            /*!< Microwire Control Register,                          Address offset: 0x00C */
    __IO uint32_t SER;             /*!< Slave Enable Register,                               Address offset: 0x010 */
    __IO uint32_t BAUDR;           /*!< Baud Rate Select,                                    Address offset: 0x014 */
    __IO uint32_t TXFTLR;          /*!< Transmit FIFO Threshold Level,                       Address offset: 0x018 */
    __IO uint32_t RXFTLR;          /*!< Receive FIFO Threshold Level,                        Address offset: 0x01C */
    __I  uint32_t TXFLR;           /*!< Transmit FIFO Level Register,                        Address offset: 0x020 */
    __I  uint32_t RXFLR;           /*!< Receive FIFO Level Register,                         Address offset: 0x024 */
    __I  uint32_t SR;              /*!< Status Register,                                     Address offset: 0x028 */
    __IO uint32_t IMR;             /*!< Interrupt Enable Register,                           Address offset: 0x02C */
    __I  uint32_t ISR;             /*!< Interrupt Status Register,                           Address offset: 0x030 */
    __I  uint32_t RISR;            /*!< Raw Interrupt Status Register,                       Address offset: 0x034 */
    __I  uint32_t TXOICR;          /*!< Transmit FIFO Overflow Interrupt Clear Register,     Address offset: 0x038 */
    __I  uint32_t RXOICR;          /*!< Receive FIFO Overflow Interrupt Clear Register,      Address offset: 0x03C */
    __I  uint32_t RXUICR;          /*!< Receive FIFO Underflow Interrupt Clear Register,     Address offset: 0x040 */
            uint32_t RESERVED0[1];    /*!< Reserved,                                                         0x044 */    
    __I  uint32_t ICR;             /*!< Interrupt Clear Register,                            Address offset: 0x048 */
    __IO uint32_t DMACR;           /*!< DMA Control Register,                                Address offset: 0x04C */
    __IO uint32_t DMATDLR;         /*!< DMA Transmit Data Level,                             Address offset: 0x050 */
    __IO uint32_t DMARDLR;         /*!< DMA Receive Data Level,                              Address offset: 0x054 */
            uint32_t RESERVED1[2];    /*!< Reserved,                                                    0x058 - 0x05C */
    __IO uint32_t DR;              /*!< Data Register,                                       Address offset: 0x060 */
            uint32_t RESERVED2[35];   /*!< Reserved,                                                    0x064 - 0x0EC */
} SPI_TypeDef;



#define MSPI0      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(0))->mspi))
#define MSPI1      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(1))->mspi))
#define MSPI2      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(2))->mspi))
#define MSPI3      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(3))->mspi))
#define MSPI4      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(4))->mspi))
#define MSPI5      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(5))->mspi))
#define MSPI6      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(6))->mspi))
#define MSPI7      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(7))->mspi))

#define SSPI0      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(0))->sspi))
#define SSPI1      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(1))->sspi))
#define SSPI2      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(2))->sspi))
#define SSPI3      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(3))->sspi))
#define SSPI4      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(4))->sspi))
#define SSPI5      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(5))->sspi))
#define SSPI6      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(6))->sspi))
#define SSPI7      ((SPI_TypeDef*)&(((ASSI_t*)ASSI(7))->sspi))



/*------------------------------------------------------------------------------------------------------*/
/*---                                Serial Peripheral Interface (SPI)                               ---*/
/*------------------------------------------------------------------------------------------------------*/
/******************************    Bit definition for SPI_CR0 register *******************************/
#define SPI_CR0_DFS_Msk               (0xFU << 0)         /*!< Data Frame Size field mask */
#define SPI_CR0_DFS_4BITS             (0x3U << 0)         /*!< 4-bit serial data transfer */
#define SPI_CR0_DFS_5BITS             (0x4U << 0)         /*!< 5-bit serial data transfer */
#define SPI_CR0_DFS_6BITS             (0x5U << 0)         /*!< 6-bit serial data transfer */
#define SPI_CR0_DFS_7BITS             (0x6U << 0)         /*!< 7-bit serial data transfer */
#define SPI_CR0_DFS_8BITS             (0x7U << 0)         /*!< 8-bit serial data transfer */
#define SPI_CR0_DFS_9BITS             (0x8U << 0)         /*!< 9-bit serial data transfer */
#define SPI_CR0_DFS_10BITS            (0x9U << 0)         /*!< 10-bit serial data transfer */
#define SPI_CR0_DFS_11BITS            (0xAU << 0)         /*!< 11-bit serial data transfer */
#define SPI_CR0_DFS_12BITS            (0xBU << 0)         /*!< 12-bit serial data transfer */
#define SPI_CR0_DFS_13BITS            (0xCU << 0)         /*!< 13-bit serial data transfer */
#define SPI_CR0_DFS_14BITS            (0xDU << 0)         /*!< 14-bit serial data transfer */
#define SPI_CR0_DFS_15BITS            (0xEU << 0)         /*!< 15-bit serial data transfer */
#define SPI_CR0_DFS_16BITS            (0xFU << 0)         /*!< 16-bit serial data transfer */

#define SPI_CR0_FRF_Msk               (0x3U << 4)         /*!< Frame Format field mask */
#define SPI_CR0_FRF_SPI               (0x0U << 4)         /*!< Motorolla SPI Frame Format */
#define SPI_CR0_FRF_SSP               (0x1U << 4)         /*!< Texas Instruments SSP Frame Format */
#define SPI_CR0_FRF_NS                (0x2U << 4)         /*!< National Microwire Frame Format */

#define SPI_CR0_CPHA                  (0x1U << 6)         /*!< Serial Clock Phase */
#define SPI_CR0_CPOL                  (0x1U << 7)         /*!< Serial Clock Polarity */

#define SPI_CR0_TMOD_Msk              (0x3U << 8)         /*!< Transfer Mode field mask */
#define SPI_CR0_TMOD_TX_AND_RX        (0x0U << 8)         /*!< Transfer & receive */
#define SPI_CR0_TMOD_TX_ONLY          (0x1U << 8)         /*!< Transmit only mode */
#define SPI_CR0_TMOD_RX_ONLY          (0x2U << 8)         /*!< Receive only mode */
#define SPI_CR0_TMOD_EEPROM_READ      (0x3U << 8)         /*!< EEPROM Read mode */

#define SPI_CR0_SLV_OE                (0x1U << 10)        /*!< Slave Output Enable */
#define SPI_CR0_SRL                   (0x1U << 11)        /*!< Shift Register Loop */

#define SPI_CR0_CFS_Msk               (0xFU << 12)        /*!< Control Frame Size field mask */
#define SPI_CR0_CFS_01_BIT            (0x0U << 12)        /*!< 1-bit Control Word */
#define SPI_CR0_CFS_02_BIT            (0x1U << 12)        /*!< 2-bit Control Word */
#define SPI_CR0_CFS_03_BIT            (0x2U << 12)        /*!< 3-bit Control Word */
#define SPI_CR0_CFS_04_BIT            (0x3U << 12)        /*!< 4-bit Control Word */
#define SPI_CR0_CFS_05_BIT            (0x4U << 12)        /*!< 5-bit Control Word */
#define SPI_CR0_CFS_06_BIT            (0x5U << 12)        /*!< 6-bit Control Word */
#define SPI_CR0_CFS_07_BIT            (0x6U << 12)        /*!< 7-bit Control Word */
#define SPI_CR0_CFS_08_BIT            (0x7U << 12)        /*!< 8-bit Control Word */
#define SPI_CR0_CFS_09_BIT            (0x8U << 12)        /*!< 9-bit Control Word */
#define SPI_CR0_CFS_10_BIT            (0x9U << 12)        /*!< 10-bit Control Word */
#define SPI_CR0_CFS_11_BIT            (0xAU << 12)        /*!< 11-bit Control Word */
#define SPI_CR0_CFS_12_BIT            (0xBU << 12)        /*!< 12-bit Control Word */
#define SPI_CR0_CFS_13_BIT            (0xCU << 12)        /*!< 13-bit Control Word */
#define SPI_CR0_CFS_14_BIT            (0xDU << 12)        /*!< 14-bit Control Word */
#define SPI_CR0_CFS_15_BIT            (0xEU << 12)        /*!< 15-bit Control Word */
#define SPI_CR0_CFS_16_BIT            (0xFU << 12)        /*!< 16-bit Control Word */

#define SPI_CR0_SPI_MODE_Msk          (0x3U << 21)        /*!< SPI Mode field mask */
#define SPI_CR0_SPI_MODE_STD          (0x0U << 21)        /*!< Standard SPI Mode */
#define SPI_CR0_SPI_MODE_DUAL         (0x1U << 21)        /*!< Dual SPI Mode */
#define SPI_CR0_SPI_MODE_QUAD         (0x2U << 21)        /*!< Quad SPI Mode */
#define SPI_CR0_SPI_MODE_OCTAL        (0x3U << 21)        /*!< Octal SPI Mode */

#define SPI_CR0_SSTE                  (0x1U << 24)        /*!< Slave Select Toggle Enable */

/******************************    Bit definition for SPI_CR1 register *******************************/
#define SPI_CR1_NDF_Msk               (0xFFFFU)           /*!< Number of Data Frames field mask */

/******************************    Bit definition for SPI_SPIENR register *******************************/
#define SPI_SPIENR_SPI_EN             (0x1U << 0)         /*!< SPI Enable */

/******************************    Bit definition for SPI_MWCR register   *******************************/
#define SPI_MWCR_MWMOD                (0x1U << 0)         /*!< Microwire Transfer Mode */
#define SPI_MWCR_MDD                  (0x1U << 1)         /*!< Microwire Control */
#define SPI_MWCR_MHS                  (0x1U << 2)         /*!< Microwire Handshaking */

/******************************    Bit definition for SPI_SER register    *******************************/
#define SPI_SER_Msk                   (0x7U << 0)         /*!< Slave Select Enable Flag field mask */
#define SPI_SER_SE0                   (0x1U << 0)         /*!< Slave 0 Select Enable Flag */
#define SPI_SER_SE1                   (0x1U << 1)         /*!< Slave 1 Select Enable Flag */
#define SPI_SER_SE2                   (0x1U << 2)         /*!< Slave 2 Select Enable Flag */

/******************************    Bit definition for SPI_BAUDR register  *******************************/
#define SPI_BAUDR_SCKDV_Msk           (0xFFFFU)           /*!< SPI Clock Divider field mask */

/******************************   Bit definition for SPI_TXFTLR register  *******************************/

/******************************   Bit definition for SPI_RXFTLR register  *******************************/

/******************************    Bit definition for SPI_TXFLR register  *******************************/

/******************************    Bit definition for SPI_RXFLR register  *******************************/

/******************************     Bit definition for SPI_SR register    *******************************/
#define SPI_SR_BUSY                   (0x1U << 0)         /*!< SPI Busy Flag */
#define SPI_SR_TFNF                   (0x1U << 1)         /*!< Transmit FIFO Not Full */
#define SPI_SR_TFE                    (0x1U << 2)         /*!< Transmit FIFO Empty */
#define SPI_SR_RFNE                   (0x1U << 3)         /*!< Receive FIFO Not Empty */
#define SPI_SR_RFF                    (0x1U << 4)         /*!< Receive FIFO Full */
#define SPI_SR_TXERR                  (0x1U << 5)         /*!< Transmission Error */
#define SPI_SR_DCOL                   (0x1U << 6)         /*!< Data Collision Error */

/******************************     Bit definition for SPI_IMR register   *******************************/
#define SPI_IMR_TXEIE                 (0x1U << 0)         /*!< Transmit FIFO Empty Interrupt Enable */
#define SPI_IMR_TXOIE                 (0x1U << 1)         /*!< Transmit FIFO Overflow Interrupt Enable */
#define SPI_IMR_RXUIE                 (0x1U << 2)         /*!< Receive FIFO Underflow Interrupt Enable */
#define SPI_IMR_RXOIE                 (0x1U << 3)         /*!< Receive FIFO Overflow Interrupt Enable */
#define SPI_IMR_RXFIE                 (0x1U << 4)         /*!< Receive FIFO Full Interrupt Enable */
#define SPI_IMR_MSTIE                 (0x1U << 5)         /*!< Multi-Master Contention Interrupt Enable */

/******************************     Bit definition for SPI_ISR register   *******************************/
#define SPI_ISR_TXEIS                 (0x1U << 0)         /*!< Transmit FIFO Empty Interrupt Status */
#define SPI_ISR_TXOIS                 (0x1U << 1)         /*!< Transmit FIFO Overflow Interrupt Status */
#define SPI_ISR_RXUIS                 (0x1U << 2)         /*!< Receive FIFO Underflow Interrupt Status */
#define SPI_ISR_RXOIS                 (0x1U << 3)         /*!< Receive FIFO Overflow Interrupt Status */
#define SPI_ISR_RXFIS                 (0x1U << 4)         /*!< Receive FIFO Full Interrupt Status */
#define SPI_ISR_MSTIS                 (0x1U << 5)         /*!< Multi-Master Contention Interrupt Status */

/******************************    Bit definition for SPI_RISR register   *******************************/
#define SPI_RISR_TXEIR                (0x1U << 0)         /*!< Transmit FIFO Empty Raw Interrupt Status */
#define SPI_RISR_TXOIR                (0x1U << 1)         /*!< Transmit FIFO Overflow Raw Interrupt Status */
#define SPI_RISR_RXUIR                (0x1U << 2)         /*!< Receive FIFO Underflow Raw Interrupt Status */
#define SPI_RISR_RXOIR                (0x1U << 3)         /*!< Receive FIFO Overflow Raw Interrupt Status */
#define SPI_RISR_RXFIR                (0x1U << 4)         /*!< Receive FIFO Full Raw Interrupt Status */
#define SPI_RISR_MSTIR                (0x1U << 5)         /*!< Multi-Master Contention Raw Interrupt Status */


/******************************   Bit definition for SPI_DMACR register   *******************************/
#define SPI_DMACR_RDMAE               (0x1U << 0)         /*!< Receive DMA Enable */
#define SPI_DMACR_TDMAE               (0x1U << 1)         /*!< Transmit DMA Enable */

/******************************  Bit definition for SPI_DMATDLR register  *******************************/

/******************************  Bit definition for SPI_DMARDLR register  *******************************/


/******************************  Bit definition for SPI_ESPICR register  ****************************/
#define SPI_ESPICR_TRANST_Msk         (0x3U << 0)         /*!< Address and instruction transfer format field mask */

#define SPI_ESPICR_ADDRL_Msk          (0xFU << 2)         /*!< Address Length field mask */
#define SPI_ESPICR_ADDRL_0BIT         (0x0U << 2)         /*!< 0-bit Address Width */
#define SPI_ESPICR_ADDRL_4BIT         (0x1U << 2)         /*!< 4-bit Address Width */
#define SPI_ESPICR_ADDRL_8BIT         (0x2U << 2)         /*!< 8-bit Address Width */
#define SPI_ESPICR_ADDRL_12BIT        (0x3U << 2)         /*!< 12-bit Address Width */
#define SPI_ESPICR_ADDRL_16BIT        (0x4U << 2)         /*!< 16-bit Address Width */
#define SPI_ESPICR_ADDRL_20BIT        (0x5U << 2)         /*!< 20-bit Address Width */
#define SPI_ESPICR_ADDRL_24BIT        (0x6U << 2)         /*!< 24-bit Address Width */
#define SPI_ESPICR_ADDRL_28BIT        (0x7U << 2)         /*!< 28-bit Address Width */
#define SPI_ESPICR_ADDRL_32BIT        (0x8U << 2)         /*!< 32-bit Address Width */
#define SPI_ESPICR_ADDRL_36BIT        (0x9U << 2)         /*!< 36-bit Address Width */
#define SPI_ESPICR_ADDRL_40BIT        (0xAU << 2)         /*!< 40-bit Address Width */
#define SPI_ESPICR_ADDRL_44BIT        (0xBU << 2)         /*!< 44-bit Address Width */
#define SPI_ESPICR_ADDRL_48BIT        (0xCU << 2)         /*!< 48-bit Address Width */
#define SPI_ESPICR_ADDRL_52BIT        (0xDU << 2)         /*!< 52-bit Address Width */
#define SPI_ESPICR_ADDRL_56BIT        (0xEU << 2)         /*!< 56-bit Address Width */
#define SPI_ESPICR_ADDRL_60BIT        (0xFU << 2)         /*!< 60-bit Address Width */

#define SPI_ESPICR_INSTL_Msk          (0x3U << 8)         /*!< Instruction Length field mask */
#define SPI_ESPICR_INSTL_0BIT         (0x0U << 8)         /*!< 0-bit (No Instruction) */
#define SPI_ESPICR_INSTL_4BIT         (0x1U << 8)         /*!< 4-bit Instruction */
#define SPI_ESPICR_INSTL_8BIT         (0x2U << 8)         /*!< 8-bit Instruction */
#define SPI_ESPICR_INSTL_16BIT        (0x3U << 8)         /*!< 16-bit Instruction */

#define SPI_ESPICR_WCYC_Msk           (0x1FU << 11)       /*!< Wait cycles field mask */



/** 
  * @brief  SPI Init structure definition  
  */
typedef struct
{
  uint16_t SPI_TransferMode;
  uint16_t SPI_DataSize;
  uint16_t SPI_CPOL;
  uint16_t SPI_CPHA;
  uint16_t SPI_BaudRatePrescaler;
  uint16_t SPI_FrameFormat;
} SPI_InitTypeDef;


/** 
  * @brief  SPI Microwire Init structure definition  
  */
typedef struct
{
  uint16_t SPI_MicrowireControlFrameSize;
  uint16_t SPI_MicrowireTransferMode;
  uint16_t SPI_MicrowireDirection;
  uint16_t SPI_MicrowireHandshaking;
} SPI_MicrowireInitTypeDef;


/** 
  * @brief  SPI Enhanced SPI Mode Init structure definition  
  */
typedef struct
{
  uint16_t SPI_EnhancedSpiTransferType;
  uint16_t SPI_EnhancedSpiInstructionLength;
  uint16_t SPI_EnhancedSpiAddressLength;
  uint16_t SPI_EnhancedSpiWaitCycles;
} SPI_EnhancedSpiInitTypeDef;

/* Exported constants --------------------------------------------------------*/

/** @defgroup SPI_Exported_Constants
  * @{
  */

/** @defgroup SPI_transfer_mode 
  * @{
  */
#define SPI_TransferMode_TxAndRx        ((uint16_t)SPI_CR0_TMOD_TX_AND_RX)
#define SPI_TransferMode_TxOnly         ((uint16_t)SPI_CR0_TMOD_TX_ONLY)
#define SPI_TransferMode_RxOnly         ((uint16_t)SPI_CR0_TMOD_RX_ONLY)
#define SPI_TransferMode_EepromRead     ((uint16_t)SPI_CR0_TMOD_EEPROM_READ)
/**
  * @}
  */


/** @defgroup SPI_data_size 
  * @{
  */
#define SPI_DataSize_4b                 ((uint16_t)SPI_CR0_DFS_4BITS)
#define SPI_DataSize_5b                 ((uint16_t)SPI_CR0_DFS_5BITS)
#define SPI_DataSize_6b                 ((uint16_t)SPI_CR0_DFS_6BITS)
#define SPI_DataSize_7b                 ((uint16_t)SPI_CR0_DFS_7BITS)
#define SPI_DataSize_8b                 ((uint16_t)SPI_CR0_DFS_8BITS)
#define SPI_DataSize_9b                 ((uint16_t)SPI_CR0_DFS_9BITS)
#define SPI_DataSize_10b                ((uint16_t)SPI_CR0_DFS_10BITS)
#define SPI_DataSize_11b                ((uint16_t)SPI_CR0_DFS_11BITS)
#define SPI_DataSize_12b                ((uint16_t)SPI_CR0_DFS_12BITS)
#define SPI_DataSize_13b                ((uint16_t)SPI_CR0_DFS_13BITS)
#define SPI_DataSize_14b                ((uint16_t)SPI_CR0_DFS_14BITS)
#define SPI_DataSize_15b                ((uint16_t)SPI_CR0_DFS_15BITS)
#define SPI_DataSize_16b                ((uint16_t)SPI_CR0_DFS_16BITS)
/**
  * @}
  */


/** @defgroup SPI_Clock_Polarity 
  * @{
  */
#define SPI_CPOL_Low                    ((uint16_t)0x00)
#define SPI_CPOL_High                   ((uint16_t)0x80)
/**
  * @}
  */


/** @defgroup SPI_Clock_Phase 
  * @{
  */
#define SPI_CPHA_1Edge                  ((uint16_t)0x00)
#define SPI_CPHA_2Edge                  ((uint16_t)0x40)
/**
  * @}
  */


/** @defgroup SPI_Frame_Format 
  * @{
  */
#define SPI_FrameFormat_SPI             ((uint16_t)SPI_CR0_FRF_SPI)
#define SPI_FrameFormat_SSP             ((uint16_t)SPI_CR0_FRF_SSP)
#define SPI_FrameFormat_Microwire       ((uint16_t)SPI_CR0_FRF_NS)
/**
  * @}
  */


/** @defgroup SPI_Microwire_Control_Frame_Size 
  * @{
  */
#define SPI_MicrowireControlFrameSize_1b      ((uint16_t)SPI_CR0_CFS_01_BIT)
#define SPI_MicrowireControlFrameSize_2b      ((uint16_t)SPI_CR0_CFS_02_BIT)
#define SPI_MicrowireControlFrameSize_3b      ((uint16_t)SPI_CR0_CFS_03_BIT)
#define SPI_MicrowireControlFrameSize_4b      ((uint16_t)SPI_CR0_CFS_04_BIT)
#define SPI_MicrowireControlFrameSize_5b      ((uint16_t)SPI_CR0_CFS_05_BIT)
#define SPI_MicrowireControlFrameSize_6b      ((uint16_t)SPI_CR0_CFS_06_BIT)
#define SPI_MicrowireControlFrameSize_7b      ((uint16_t)SPI_CR0_CFS_07_BIT)
#define SPI_MicrowireControlFrameSize_8b      ((uint16_t)SPI_CR0_CFS_08_BIT)
#define SPI_MicrowireControlFrameSize_9b      ((uint16_t)SPI_CR0_CFS_09_BIT)
#define SPI_MicrowireControlFrameSize_10b     ((uint16_t)SPI_CR0_CFS_10_BIT)
#define SPI_MicrowireControlFrameSize_11b     ((uint16_t)SPI_CR0_CFS_11_BIT)
#define SPI_MicrowireControlFrameSize_12b     ((uint16_t)SPI_CR0_CFS_12_BIT)
#define SPI_MicrowireControlFrameSize_13b     ((uint16_t)SPI_CR0_CFS_13_BIT)
#define SPI_MicrowireControlFrameSize_14b     ((uint16_t)SPI_CR0_CFS_14_BIT)
#define SPI_MicrowireControlFrameSize_15b     ((uint16_t)SPI_CR0_CFS_15_BIT)
#define SPI_MicrowireControlFrameSize_16b     ((uint16_t)SPI_CR0_CFS_16_BIT)
/**
  * @}
  */


/** @defgroup SPI_Microwire_Transfer_Mode 
  * @{
  */
#define SPI_MicrowireTransferMode_NonSequential   ((uint16_t)0x00)
#define SPI_MicrowireTransferMode_Sequential      ((uint16_t)0x01)
/**
  * @}
  */


/** @defgroup SPI_Microwire_Direction 
  * @{
  */
#define SPI_MicrowireDirection_Receive        ((uint16_t)0x00)
#define SPI_MicrowireDirection_Transmit       ((uint16_t)0x02)
/**
  * @}
  */


/** @defgroup SPI_Microwire_Handshaking 
  * @{
  */
#define SPI_MicrowireHandshaking_Enable       ((uint16_t)0x04)
#define SPI_MicrowireHandshaking_Disable      ((uint16_t)0x00)
/**
  * @}
  */


/** @defgroup SPI_SpiMode 
  * @{
  */
#define SPI_SpiMode_Standard   (SPI_CR0_SPI_MODE_STD)
#define SPI_SpiMode_Dual       (SPI_CR0_SPI_MODE_DUAL)
#define SPI_SpiMode_Quad       (SPI_CR0_SPI_MODE_QUAD)
/**
  * @}
  */


/** @defgroup SPI_EnhancedSpi_TransferType 
  * @{
  */
#define SPI_EnhancedSpiTransferType_0         ((uint16_t)0x00)
#define SPI_EnhancedSpiTransferType_1         ((uint16_t)0x01)
#define SPI_EnhancedSpiTransferType_2         ((uint16_t)0x02)
/**
  * @}
  */


/** @defgroup SPI_EnhancedSpi_InstructionLength 
  * @{
  */
#define SPI_EnhancedSpiInstructionLength_0b   ((uint16_t)SPI_ESPICR_INSTL_0BIT)
#define SPI_EnhancedSpiInstructionLength_4b   ((uint16_t)SPI_ESPICR_INSTL_4BIT)
#define SPI_EnhancedSpiInstructionLength_8b   ((uint16_t)SPI_ESPICR_INSTL_8BIT)
#define SPI_EnhancedSpiInstructionLength_16b  ((uint16_t)SPI_ESPICR_INSTL_16BIT)
/**
  * @}
  */


/** @defgroup SPI_EnhancedSpi_AddressLength 
  * @{
  */
#define SPI_EnhancedSpiAddressLength_0b       ((uint16_t)SPI_ESPICR_ADDRL_0BIT)
#define SPI_EnhancedSpiAddressLength_4b       ((uint16_t)SPI_ESPICR_ADDRL_4BIT)
#define SPI_EnhancedSpiAddressLength_8b       ((uint16_t)SPI_ESPICR_ADDRL_8BIT)
#define SPI_EnhancedSpiAddressLength_12b      ((uint16_t)SPI_ESPICR_ADDRL_12BIT)
#define SPI_EnhancedSpiAddressLength_16b      ((uint16_t)SPI_ESPICR_ADDRL_16BIT)
#define SPI_EnhancedSpiAddressLength_20b      ((uint16_t)SPI_ESPICR_ADDRL_20BIT)
#define SPI_EnhancedSpiAddressLength_24b      ((uint16_t)SPI_ESPICR_ADDRL_24BIT)
#define SPI_EnhancedSpiAddressLength_28b      ((uint16_t)SPI_ESPICR_ADDRL_28BIT)
#define SPI_EnhancedSpiAddressLength_32b      ((uint16_t)SPI_ESPICR_ADDRL_32BIT)
#define SPI_EnhancedSpiAddressLength_36b      ((uint16_t)SPI_ESPICR_ADDRL_36BIT)
#define SPI_EnhancedSpiAddressLength_40b      ((uint16_t)SPI_ESPICR_ADDRL_40BIT)
#define SPI_EnhancedSpiAddressLength_44b      ((uint16_t)SPI_ESPICR_ADDRL_44BIT)
#define SPI_EnhancedSpiAddressLength_48b      ((uint16_t)SPI_ESPICR_ADDRL_48BIT)
#define SPI_EnhancedSpiAddressLength_52b      ((uint16_t)SPI_ESPICR_ADDRL_52BIT)
#define SPI_EnhancedSpiAddressLength_56b      ((uint16_t)SPI_ESPICR_ADDRL_56BIT)
#define SPI_EnhancedSpiAddressLength_60b      ((uint16_t)SPI_ESPICR_ADDRL_60BIT)
/**
  * @}
  */


/** @defgroup SPI_NSS_definition 
  * @{
  */
#define SPI_NSS_0       (0x01)
/**
  * @}
  */


/** @defgroup SPI_flags_definition 
  * @{
  */
#define SPI_FLAG_BUSY   ((uint8_t)SPI_SR_BUSY)
#define SPI_FLAG_TFNF   ((uint8_t)SPI_SR_TFNF)
#define SPI_FLAG_TFE    ((uint8_t)SPI_SR_TFE)
#define SPI_FLAG_RFNE   ((uint8_t)SPI_SR_RFNE)
#define SPI_FLAG_RFF    ((uint8_t)SPI_SR_RFF)
#define SPI_FLAG_TXERR  ((uint8_t)SPI_SR_TXERR)
#define SPI_FLAG_DCOL   ((uint8_t)SPI_SR_DCOL)
/**
  * @}
  */


/** @defgroup SPI_interrupts_definition
  * @{
  */
#define SPI_IT_TXE      (0x1 << 0)
#define SPI_IT_TXO      (0x1 << 1)
#define SPI_IT_RXU      (0x1 << 2)
#define SPI_IT_RXO      (0x1 << 3)
#define SPI_IT_RXF      (0x1 << 4)
#define SPI_IT_MST      (0x1 << 5)
/**
  * @}
  */


/** @defgroup SPI_DMA_Requests 
  * @{
  */
#define SPI_DMAReq_Rx             0x01
#define SPI_DMAReq_Tx             0x02
/**
  * @}
  */ 

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState_t NewState);
void SPI_TransferModeConfig(SPI_TypeDef* SPIx, uint16_t SPI_TransferMode);
void SPI_SlaveOutputCmd(SPI_TypeDef* SPIx, FunctionalState_t NewState);
void SPI_NSSConfig(SPI_TypeDef* SPIx, uint32_t SPI_NSS, FunctionalState_t NewState);
void SPI_NSSToggleModeCmd(SPI_TypeDef* SPIx, FunctionalState_t NewState);
void SPI_ReceiveDataLengthConfig(SPI_TypeDef* SPIx, uint32_t DataLength);
void SPI_MicrowireConfig(SPI_TypeDef* SPIx, SPI_MicrowireInitTypeDef* SPI_MicrowireInitStruct);
void SPI_MicrowireStructInit(SPI_MicrowireInitTypeDef* SPI_MicrowireInitStruct);
void SPI_SpiModeConfig(SPI_TypeDef* SPIx, uint32_t SPI_SpiMode);
void SPI_EnhancedSpiConfig(SPI_TypeDef* SPIx, SPI_EnhancedSpiInitTypeDef* SPI_EnhancedSpiInitStruct);
void SPI_EnhancedSpiStructInit(SPI_EnhancedSpiInitTypeDef* SPI_EnhancedSpiInitStruct);
uint16_t SPI_ReadData(SPI_TypeDef* SPIx);
void SPI_WriteData(SPI_TypeDef* SPIx, uint16_t data);
FlagStatus_t SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint8_t SPI_FLAG);
void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState_t NewState);
ITStatus_t SPI_GetRawITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT);
ITStatus_t SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT);
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_IT);
void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint8_t Threshold);
void SPI_TxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint8_t Threshold);
uint8_t SPI_GetRxFIFOLevel(SPI_TypeDef* SPIx);
uint8_t SPI_GetTxFIFOLevel(SPI_TypeDef* SPIx);
void SPI_DMARxReqLevelConfig(SPI_TypeDef* SPIx, uint8_t DMARxReqLevel);
void SPI_DMATxReqLevelConfig(SPI_TypeDef* SPIx, uint8_t DMATxReqLevel);
void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState_t NewState);
void SPI_RxdSampleDelayConfig(SPI_TypeDef* SPIx, uint8_t DelayValue);

/**
  * @}
  */



#endif